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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Decade Counter
MC74HC4017
16 1
High-Performance Silicon-Gate CMOS
The MC74HC4017 is identical in pinout to the standard CMOS MC14017B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC4017 uses a five stage Johnson counter and decoding logic to provide high-speed operation. This device also has an active-high, as well as active-low clock input. * Output Drive Capability: 10 LSTTL Loads * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2 to 6 V * Low Input Current: 1 A * High Noise Immunity Characteristic of CMOS Devices * In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 176 FETs or 44 Equivalent Gates
N SUFFIX PLASTIC PACKAGE CASE 648-08
16 1
D SUFFIX SOIC PACKAGE CASE 751B-05
ORDERING INFORMATION MC74HCXXXXN MC74HCXXXXD Plastic SOIC
LOGIC DIAGRAM
PIN ASSIGNMENT
Q5 3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RESET CLOCK CLOCK ENABLE CARRY OUT Q9 Q4 Q8
CLOCK CLOCK ENABLE
14 13
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 DECADE OUTPUTS
Q1 Q0 Q2 Q6 Q7 Q3 GND
2 4 7 10 1 5 6 9 11
12
CARRY OUT
RESET
15
PIN 16 = VCC PIN 8 = GND
10/95
(c) Motorola, Inc. 1995
1
REV 6
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* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
RECOMMENDED OPERATING CONDITIONS
MAXIMUM RATINGS*
MC74HC4017
Symbol
Vin, Vout
Symbol
Symbol
VCC
Vout
Tstg
ICC
Iout
VCC
Vin
PD
TL
VOH
tr, tf
Iin
VOL
ICC
TA
VIH
VIL
Iin
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Storage Temperature
Power Dissipation in Still Air
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time (Figure 1)
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
Parameter
Plastic DIP SOIC Package
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| 20 A
Vin = VCC or GND Iout = 0 A
Vin = VCC or GND
Vin = VIH or VIL |Iout| |Iout|
Vin = VIH or VIL |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v
v
v
v
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Test Conditions
- 0.5 to VCC + 0.5
- 1.5 to VCC + 1.5
- 65 to + 150
- 0.5 to + 7.0
2 - 55 Min 2.0 Value
v 4.0 mA v 5.2 mA
v 4.0 mA v 5.2 mA
0 0 0
0
50
25
20
260
750 500
+ 125
1000 500 400
VCC
Max
6.0
VCC V
6.0
6.0
4.5 6.0
2.0 4.5 6.0
4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
- 55 to 25_C
0.1
1.5 3.15 4.2
0.26 0.26
3.98 5.48
0.1 0.1 0.1
1.9 4.4 5.9
0.3 0.9 1.2
8
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 1.0 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 80
v
1.0 1.5 3.15 4.2 0.40 0.40 3.70 5.20 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2
160
v
Unit
A A V V V V
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NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL tPLH fmax CPD Cin Power Dissipation Capacitance (Per Package)* Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 8 and 9) Maximum Propagation Delay, Clock Enable to Q (Figures 4 and 9) Maximum Propagation Delay, Reset to Carry Out (Figures 3 and 9) Maximum Propagation Delay, Reset to Q (Figures 3 and 9) Maximum Propagation Delay, Clock to Carry Out (Figures 2 and 9) Maximum Propagation Delay, Clock to Q (Figures 1 and 9) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 9) Parameter
* Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Maximum Propagation Delay, Clock Enable to Carry Out (Figures 5 and 9)
3 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- - 55 to 25_C Typical @ 25C, VCC = 5.0 V 250 50 43 250 50 43 230 46 39 230 46 39 230 46 39 230 46 39 4.0 20 24 10 75 15 13 Guaranteed Limit 315 63 54 315 63 54 290 58 49 290 58 49 290 58 49 290 58 49 3.2 16 19 10 95 19 16 35 375 75 64 375 75 64 345 69 59 345 69 59 345 69 59 345 69 59 110 22 19 2.6 13 15 10
v 85_C v 125_C
MC74HC4017
MOTOROLA MHz Unit pF pF ns ns ns ns ns ns ns
MC74HC4017
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I
TIMING REQUIREMENTS (Input tr = tf = 6 ns)t
Guaranteed Limit Symbol tsu Parameter VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C 50 10 9 50 10 9 50 10 9
v 85_C v 125_C
65 13 11 65 13 11 65 13 11 75 15 13 75 15 13 75 15 13
Unit ns
Minimum Setup Time, Clock Enable to Clock (Figure 6)
tsu
Minimum Setup Time, Clock Enable to Clock (Inhibit Count) (Figure 6) Minimum Hold Time, Clock to Clock Enable (Figure 6) Minimum Recovery Time, Reset to Clock (Figure 7) Minimum Pulse Width, Clock Input (Figure 2)
ns
th
ns
trec
100 20 17 80 16 14 80 16 14 80 16 14
125 25 21 100 20 17 100 20 17 100 20 17
150 30 26 120 24 20 120 24 20 120 24 20
ns
tw
ns
tw
Minimum Pulse Width, Reset Input (Figure 3)
ns
tw
Minimum Pulse Width, Clock Enable Input (Figure 4) Maximum Input Rise and Fall Times (Figure 1)
ns
tr, tf
1000 500 400
1000 500 400
1000 500 400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
FUNCTION TABLE
Clock L X X
Clock Enable X H X L X
Reset L L H L L L L
Output State* no change no change reset counter, Q0 = H, Q1 - Q9 = L, C0 = H advance to next state no change no change advance to next state
X H
X = Don't care * Carry Out = H for Q0, Q1, Q2, Q3, or Q4 = H; Carry Out = L otherwise.
PIN DESCRIPTIONS
INPUTS Clock (Pin 14) Counter clock input. While Clock Enable is low, a low-to- high transition on this input advances the counter to its next state. Reset (Pin 15) Asynchronous counter reset input. A high level at this input initializes the counter and forces Q0 and Carry Out to a high, Q1-Q9 are forced to a low level. Clock Enable (Pin 13) Active-low clock enable input. A low level on this input allows the device to count. A high level on this input inhibits the counting operation. This input may also be used as a negative-edge clock input. using Clock (Pin 14) as an active-high enable pin. OUTPUTS Q0 - Q9 (Pins 3, 2, 4, 7, 10, 1, 5, 6, 9, 11) Decoded decade counter outputs. Each of these outputs is high for one clock period only. Carry Out (Pin 12) Cascading output pin. This output is used either as a cascading output or a symmetrical divide-by-ten output. This output goes low when a count of five is reached and high when the counter advances to zero or when reset. When the counters are cascaded this output provides a rising-edge signal for the clock input of the next counter stage.
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4017
SWITCHING WAVEFORMS
tr 90% 50% 10% tw 1/fmax tPLH Q 90% 50% 10% tTLH tTHL tw VCC 50% VCC RESET 50% GND tw tPHL CLOCK ENABLE Q GND tPLH 50% tPHL tPHL tPLH CARRY OUT 50% tf VCC CLOCK GND tw tPHL 50% GND VCC
CLOCK
Figure 2.
Figure 1.
Figure 4.
Q1-Q9 50% VCC tPLH GND Q0, CARRY OUT 50% CLOCK ENABLE 50% GND tsu CLOCK th VCC 50% GND VCC CLOCK ENABLE tPHL CARRY OUT 50% 50% GND tPLH Q0 - Q9, CARRY OUT tTLH 90% 10% tTHL VALID VCC
Figure 3.
Figure 6.
Figure 5.
Figure 8.
TEST POINT OUTPUT VCC 50% CLOCK trec RESET 50% VCC GND * Includes all probe and jig capacitance GND DEVICE UNDER TEST CL*
Figure 7.
Figure 9. Test Circuit
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC74HC4017
TIMIING DIAGRAM
CLOCK CLOCK ENABLE RESET Q0
Q1 Q2 Q3 Q4
Q5 Q6
Q7 Q8 Q9 CARRY OUT
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4017
EXPANDED LOGIC DIAGRAM
D
Q 3 C Q R Q0
RESET
15
2
Q1
D C R
Q Q
4
Q2
7
Q3
10 CLOCK 14 1
Q4
Q5
5 CLOCK 13 ENABLE D C R 9 Q Q
Q6
6
Q7
Q8
D C R
Q Q
11
Q9
12 CARRY OUT
D C R
Q Q
High-Speed CMOS Logic Data DL129 -- Rev 6
7
MOTOROLA
MC74HC4017
TYPICAL APPLICATIONS
VCC HC4017
/5
1 2 3
Q5
/2 /6 /7 /3
4 5 6 7 8
VCC 16 15 RESET Q1 14 CLOCK Q0 CLOCK 13 Q2 ENABLE 12 Q6 CARRY OUT 11 Q7 Q9 10 Q4 Q3 9 Q8 GND
OSC. / 10 /9 /4 /8 1/6 HC04 OUTPUT (NO FEEDBACK REQUIRED)
BUFFER (OPTIONAL TO PREVENT SPURIOUS RESET.)
Figure 10 shows a divide by 2 through 10 circuit using one HC4017. Please note that since Reset is asynchronous, the output pulse widths are narrow. Figure 10. /2 Through / 10 Circuit
R C CE Q0 HC4017 Q1 Q8 Q9 C CE Q0
R HC4017 Q1 Q8 Q9 C CE Q1
R HC4017 Q8 Q9
9 DECODED OUTPUTS
8 DECODED OUTPUTS
8 DECODED OUTPUTS
CLOCK FIRST STAGE
HC08 INTERMEDIATE STAGES
HC08 LAST STAGE
Figure 11 shows a technique for cascading the counters to extend the number of decoded output states. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay). Figure 11. Counter Expansion
MOTOROLA
8
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4017
OUTLINE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
B
1 8
-A -
16 9
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
-A -
16 9
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
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High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
9
*MC74HC4017/D*
MC74HC4017/D MOTOROLA

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